In the semiconductor art, it is desirable to add RAM storage onto an integrated circuit which also comprises other circuitry, for example, for microprocessor circuits (MPUs,) microcontroller circuits (MCUs), digital signal processors (DSPs), RF or filter circuitry which uses stored data or parameteric information, analog-to-digital converters and the like, or other advanced circuitry which requires data or program storage to be rapidly accessible by programmable or logic circuitry. In the prior art this need is addressed by so-called “embedded” RAM circuits which may comprise multiple transistor SRAM cells, or transistors plus capacitive storage cells, and sometimes storage cells, each cell formed from one transistor and a capacitor, so-called “1T” RAM bit cells. For example, the paper entitled “The Ideal SoC Memory: 1T-SRAM”, Leung et al., published in the Proceedings of the Annual IEEE International ASIC Conference and Exhibits, 2000, pp. 32-36, describes the use of a one transistor storage cell having a capacitor and using transparent (hidden) refresh techniques to implement a “SRAM” cell.
In a semiconductor device with embedded RAM circuits, the device may be divided into different areas so that compatible, but differing, process steps and materials may be used to implement devices having different physical characteristics. For example, a biCMOS semiconductor device peripheral circuitry, which includes large driver circuits, may incorporate bipolar transistors for the driving buffers while the internal or core logic circuitry may be only CMOS technology, which is implemented in a planar technology. In other known processes, other embedded circuitry may be fabricated as SOI (silicon-on-insulator) or SIMOX devices, which lie above the planar circuitry, which is formed at the surface of the silicon substrate. Such integrated or embedded technologies are required to implement the systems on an integrated circuit (SOICs) or systems on a chip (SOC), or the highly integrated microprocessors and signal processors that are currently being designed or which will be designed in the future.
Capacitors are elements that are used in semiconductor devices for storing electrical charge. The presence of certain levels of stored charge, or the absence of the stored charge, may represent data values, for example, data values ‘0’ and ‘1’ are used in a typical binary circuit. In a semiconductor memory device, or in a portion of a semiconductor integrated circuit including an embedded memory array, a capacitor may be used as a data storage element which is read and/or written by an access transistor which couples the capacitor storage element to bit lines which may be used to supply write data for storage, or in a read mode, sense the stored charge and interpret that as read data. In some memory arrays the transistor and capacitor are arranged to form a 1T-RAM bit cell. The most desirable form of memory storage is “static” or SRAM, many different cells can be fabricated as SRAM cells, however, these cells require usually 6 or even 8 transistors to implement, which take up substantially more area than a similar capacitive storage cell. The capacitor may have to be periodically refreshed by reading the cell and writing back the charge stored, in this case the cell is typically referred to as a “dynamic” RAM or DRAM cell. If, however, a capacitor can be used in a 1T-RAM bit cell where the capacitor refresh is required so infrequently as to allow it to be hidden from the user by automatic on-board circuitry and performed during other operations (a so-called “hidden” or “transparent” refresh), it may be referred to as “pseudo-static” RAM cell or just a 1T-RAM (one transistor RAM) bit cell.
1T-RAM bit cells have a great advantage over multiple transistor SRAM cells in that the area used to implement them is small, so that a much greater amount of memory may be provided in a small silicon area. This cell area advantage is particularly important in embedded RAM arrays for system on a chip (SoC or SOIC) or application specific IC (ASIC) applications. U.S. Pat. No. 6,638,813, entitled “Method of Forming a Composite Spacer to Eliminate Polysilicon Stringers Between Elements in a Pseudo SRAM Cell,” to Tzeng et al.; U.S. Pat. No. 6,528,422, entitled “Method to Modify 0.25 μM 1T-RAM by Extra Resist Protect Oxide (RPO) Blocking”, to Huang et al.; and U.S. Pat. No. 6,420,226, entitled “Method to Defining a Buried Stack Capacitor Structure for a One Transistor RAM Cell,” to Chen et al.; each incorporated herein by reference, and each assigned to the assignee of the present invention, describe various 1T-RAM bit cells using capacitor storage elements.
Macro cells may be created which include 1T-RAM bit cells and other logic circuitry such as drivers, buffers, clock fan out circuits, and other peripheral circuitry which does not require capacitors; the transistors used in these other related circuits may be the same or different from the storage cells; these macro cells are organized together to form a functional circuit so as to form application specific integrated circuits (ASICs) by circuit designers, by providing predetermined functions in the form of proven and reusable macro cells, the design time required for designing an integrated circuit performing a new or modified function is significantly reduced. Macro cells can be as simple as a few transistors, or as complex as an embedded RAM, ROM, flash or EEPROM array, a register file or FIFO, or a macro cell may be a complete DSP device including embedded ROM and RAM and a programmable processor.
Capacitors in semiconductor devices are formed by providing at least two conductive plates separated by an insulator or dielectric layer, or sometimes separated by multiple layers of insulating material. The capacitance, or the measure of the amount of charge that will be held by the capacitor for an applied voltage potential across the plates, will depend on many parameters such as the area of the plates, the distance between the plates, and the dielectric constant value for the insulator between the plates, as examples. In addition to their use as a storage element, capacitors embedded on integrated circuits have many other applications, including as an element in RC networks, for filtering circuits, for analog-to-digital and digital-to-analog converters, for switched capacitor networks, and they may be used with any other circuit arrangement which uses capacitance as a circuit element.
One particularly important type of storage capacitor is a metal-insulator-metal (MIM) capacitor. This capacitor is formed from a stack of materials including a metal or polysilicon first electrode or plate, an insulator which may incorporate various dielectrics including high-k dielectric materials, and a second electrode or plate which again may be a metal or polysilicon material. An advantage of a MIM capacitor for integration for embedded applications is that the MIM capacitor can be formed in the interlevel insulator layers above the silicon substrate, so that the MIM capacitor may be efficiently provided without consuming valuable active device area on the substrate itself, instead the MIM capacitor may be provided in the area overlying the substrate so that planar MOS transistor devices may be placed underneath it, or if an SOI or SIMOX approach is used, even above it. Often, at least one of the conductive plates is formed in a metallization layer or metal interconnect layer of the semiconductor device. Another capacitor plate may be formed in the polysilicon or “poly” layers which are typically formed closer to the surface of the substrate; of course the MIM capacitor can be formed in layers far above the substrate as well. Planar or “in substrate” capacitors are also known in the art. U.S. Pat. No. 6,720,232, to Tu, et al., entitled “Method of Fabricating an Embedded DRAM for Metal-Insulator-Metal (MIM) Capacitor Structure,” assigned to the assignee of the present invention and also hereby incorporated by reference, describes one method for forming MIM capacitors in the interlevel insulator layers above the substrate for RAM bit cells.
It is known in the prior art that the capacitance of an integrated capacitor may be increased if the effective area of the plates is increased by texturing the plates. Various materials and techniques are known to create rough, or textured surfaces for use in a capacitor, for example, so-called HSG or hemispherical grain material may be created by a deposition and special anneal or by chemically treating or etching a material after it is deposited. These approaches may be applied to a MIM capacitor.
Performance of a capacitor may be further enhanced by the use of various so-called high-k dielectrics in the insulating layer, for example. The dielectric conventionally used in the semiconductor art is silicon dioxide, which has a dielectric constant “k” of 3.9. Dielectrics with a dielectric constant greater than 3.9 are therefore referred to as “high-k” dielectrics. A paper entitled “High-Performance MIM Capacitor using ALD High-k HfO2—Al2O3 Laminate Dielectrics,” Ding et al, IEEE Electron Device Letters, Vol. 24, No. 12, December 2003, pp. 730-732, for example, describes a MIM capacitor with a dielectric formed by two materials, hafnium oxide (HfO2) and aluminum oxide (Al2O3), which are in a laminated “sandwich” of thin layers to using atomic layer deposition (ALD) techniques. A paper entitled “High-Density MIM Capacitors using AlTaOx Dielectrics”, Yang et al., IEEE Electron Device Letters, Vol. 24, No. 5, May 2003, pp. 306-308, similarly describes desirable results using aluminum tantalum oxide dielectric material in a MIM storage capacitor for integrated circuits.
A prior art semiconductor device 100 including a MIM capacitor storage bit cell is shown in a cross section (drawn for illustration, and no figures in this description are to scale and should be considered as descriptive only) in FIG. 1. The semiconductor device 100 includes a substrate 101 having a memory region and a logic region. The substrate may be, for example, a silicon substrate having a 100 or other known crystal orientation, a silicon-germanium substrate (SiGe) or other substrates known and used in the semiconductor art. The silicon substrate could be a layer of silicon deposited or grown over an insulator in a silicon-on-insulator (SOI) process, for example.
The substrate has doped well areas formed within it, N-type wells 103 and P-type well 105 are shown in FIG. 1. These doped wells may be formed using various known semiconductor processing steps, including an ion implant of the doping ions followed by a thermal anneal, or known other process steps may be used. These wells could be formed before the other features shown in the cross section, or using a high energy through-layer implant of ions through layers, after deposition of the gate dielectric layer, for example. One or more elements in group V on the periodic table can be used as dopants for the N-well, as is known in the art, on one or more elements of group III in the periodic table can be used as dopants for the P-well, also as is known in the art. Inert material can also be implanted to improve the electrical characteristics of the devices as is known in the art.
Shallow trench isolation regions 107 are formed within the substrate and have a depth somewhat less than the depth of the wells 103 and 105. As is known in the prior art, shallow trench isolation regions or STI provide many advantages including electrical isolation of the semiconductor regions separated by the STI regions. Shallow trench isolation regions 107 are filled with an insulating material which may be, for example, a high density plasma oxide (HDP) material.
A plurality of transistors are formed in and over the substrate 101, transistors 113 and 115 in the logic region form planar MOS transistors, which may be used for a variety of logical and electrical functions. Transistor 113 is a P-channel device having a source and drain region formed in the N-well 103 and separated by a channel covered with a gate dielectric or oxide, and transistor 115 is an N-channel device formed in P-well 105 having a source and drain region separated by a channel covered with a gate dielectric or gate oxide. Each transistor 113 and 115 also has a polysilicon or metal gate terminal, and in FIG. 1 the source, drain and gate regions are all shown with a resistance lowering Cobalt salicide layer overlying, or strapping, the source, drain and gate conductors, this is an optional feature which will result in better device performance. STI region 107 provides a connectivity site for conductive metal layer 151 to contact the polysilicon conductor 111 by means of a via stack 131 formed in interlevel oxide layers 153, 155 and 157. Conductive metal layer 149 is coupled electrically to the N-channel planar transistor 115 by a via stack 129 extending through interlevel oxide layers 153, 155, and 157. Transistors 113 and 115 are a P and N-channel pair of CMOS logic transistors and may form an inverter, for example, but may also be used separately or used as diodes, pass transistors or for other functions as is known in the art by changing the connections made at the metallization layer.
Transistor 119 formed in N-well 103 in the memory region comprises the access transistor of the RAM storage cell shown in the figure. Although a single access transistor and a capacitor are shown in the figure, a practical device might have many thousands of these cells in a typical arrangement. Storage MIM capacitor 121 is formed above the substrate in the interlevel oxide layers 155 and 153 and has a contact plug 123 through interlevel oxide 157 which provides electrical contact to a source/drain region of the P-channel transistor 119. The capacitor is a metal-insulator-metal (MIM) or metal-insulator-semiconductor (MIS) capacitor formed as a vertical capacitor as shown. Contact plug 123 provides electrical contact to the bottom plate of the MIM and via 133 forms electrical contact to the top plate of the MIM, which is coupled electrically to conductive metal layer 143.
The prior art device depicted in FIG. 1 provides planar logic transistors and an embedded memory circuit within a single integrated circuit device. The process steps for making the prior art device of FIG. 1 will now be briefly described.
FIG. 2 depicts a step early in the process of manufacturing the embedded memory cell shown in FIG. 1. In FIG. 2, substrate 101 is shown, again in an illustrative cross-section and not drawn to scale. Substrate 101 is a conventionally used silicon monocrystalline substrate. Other known semiconductor substrate materials may be used. Substrate 101 may be a bulk silicon substrate, or a silicon-on-insulator (SOI) region deposited over an insulator. In the example shown, the substrate 101 is a P-type material, other substrate types known to the art may be used. A layer of pad oxide 102 is formed on substrate 101. Typically, pad oxide 102 is a conventional pad oxide material such as silicon dioxide and may be grown or deposited, other approaches may be used such as composite oxide including TEOS and silicon dioxide or nitride oxide, or a gate dielectric. The pad oxide 102 may be, for example, thermally grown in an oxygen-steam ambient at a temperature between 800 and 1,000 degrees C. The pad oxide may be a variety of thicknesses, for example, it may be a thickness of from about 30 to about 300 Angstroms. Other oxidation processes could be used to produce the pad oxide including oxidation in a dry oxygen and anhydrous hydrogen chloride, in high or low pressure environments, and in high or low temperature environments. Rapid thermal oxidation may also be used.
Layer 104 is a nitride layer formed over the pad oxide 102. Layer 104 is, for example, of silicon nitride (Si3N4) and can be deposited using conventional deposition for nitride layers, including LPCVD or PECVE procedures, for example, at pressures between about 300 milliTorr and 400 milliTorr at a temperature between about 400 and 800 degrees C. using gases such as NH4 and SiH4 as reactants. Alternative approaches include using LPCVD and PECVD equipment, using as reactants other gases such as dichlorosiliane (SiCl2H2) and ammonia (NH3).
In FIG. 3, the shallow trench isolation regions (STI) 107 are depicted as initially formed by a conventional etching process after a conventional photolithographic patterning step (not shown) is used. For example, plasma etching may be used to remove the nitride, pad oxide and etch the substrate in regions 107. In a plasma etch process, as is conventionally known in the art, a first electrode is provided in a processing chamber of a conventional plasma etch reactor and the substrate is positioned upon the electrode. A second electrode is provided which is spaced apart and is opposite from the first, for example, the second electrode may be in or attached to the lid of the processing chambers, although other arrangements are also used. A gaseous medium for the plasma is flowed through the chamber and energy in the form of a radio frequency or RF voltage, which may include components having various frequencies, is applied across the two electrodes to create a gaseous discharge that ionizes the medium and forms a plasma, the ions bombard and etch the wafer. The gases and RF frequencies may be varied, as is known in the art, to produce a highly selective and anisotropic etch. Typically, a dry etch is used where the wafer is exposed to etchant gases in the plasma chamber including, for example, CF4, CHF3 (Freon), SF6 of NF3. Other gases such as N2, O2 and Ar may be used. The depth of the STI trench can vary, however, depths of 1000 to 5000 Angstroms are used.
FIG. 3 depicts the substrate 101 after the STI regions are filled with a trench oxide 106. Trench oxide 106 can be formed conventionally by CVD of silicon dioxide filling the trenches 107 and further overlying the remaining nitride layer. Alternatively, PECVD deposition may be used to form oxide layer 106. The trench oxide may be formed in a PECVD reaction chamber using temperatures from about 200 to 350 degrees C., for SiH4/O2 or SiH4/N20 precursors. The thickness of the trench oxide layer is variable but may be, for example, about 3000-5000 Angstroms.
FIG. 3 depicts substrate 101 after the excess trench oxide is removed from the STI trenches and the substrate by chemical mechanical polishing, or CMP. In CMP, the material is removed and the surface is planarized exposing the surface to a polish or grit material which is applied with rotation and pressure to remove the excess material. Other conventional CMP steps can be used as is known in the art. The oxide layer 106 is removed to a certain desired thickness, nitride layer 104 is removed to leave a desired amount of oxide layer 106 in the STI regions above the surface of substrate 101.
In FIG. 3, the substrate is shown after the deposition of gate dielectric layer 122 and gate electrode material for electrodes 111, 113, 115, 117, 119; and following the pattern and etch to form the individual gate electrodes having sidewalls. Conventional methods are used to deposit a gate oxide or gate dielectric over the substrate and the trench isolation regions, the gate polysilicon is deposited over the gate oxide, a patterning step is performed to form protected and non-protected areas, and conventional etching steps are used to remove the gate conductor material and the gate oxide material in the non-protected areas, the hardmask or hardened photoresist is then removed from the gate and polysilicon conductors to form the structure shown in FIG. 3. For example, the gate oxide formation may result in an SiO2 layer that is from 20 to 70 Angstroms thick.
Following the formation of the gate oxide or dielectric, polysilicon or metal gate conductor material is deposited over the oxide to form the gate electrode layer, this may be a layer of polysilicon with a thickness of from about 1500 to about 2500 Angstroms thick. This polysilicon layer and the underlying gate dielectric are then patterned using conventional photomask and photoresist steps as known in the art and the unnecessary material is removed leaving the gate conductors 113, 115 and 119 and their underlying gate oxides, as well as the polysilicon level conductors 111, 115 and 117. The gate electrodes overlying the trenches will not, of course, act as device gates in the region shown in the cross section, as they lie over the trench isolation regions and not active area, but instead they provide connectivity areas at the polysilicon level to allow other levels of conductors to be connected to the gate polysilicon layer.
In FIG. 4, an important processing step is shown for producing the memory area of the integrated circuit. Because the logic section of the device may have, if desired, certain different physical characteristics than that of the memory section, a photomask (not shown) is used to produce a protective patterned photoresist layer 112 over the logic region area, prior to the implant for the lightly doped drain and source diffusions 114 of the memory area, this implantation step is shown in FIG. 4. The protective layer 112 is formed using a photomask sometimes known as the cell lightly doped drain mask, or “CLDD” mask, and is used to form the photoresist coating 112 that protects the logic area devices during the cell lightly doped drain implant steps. After source and drain doping for the memory area of the device is complete, a second similar photomask will be used to form a photoresist layer (not shown) over the memory area and to protect the memory area while a lightly doped drain diffusion using different ion implantation energies and/or different doping materials will be performed in the logic area of the device. This asymmetric photolithographic processing approach enables the memory area and the logic area transistors of a single device to have optimal physical characteristics that are different for the two regions in a single, compatible process for manufacture. In particular, the two regions are subjected to separate and different ion implantation steps for the source and drain lightly doped implants.
As the gate polysilicon electrodes are formed prior to the source and drain region implants, the gates are said to be self-aligned, the gate electrodes 113, 115 and 119 form part of the mask over the substrate which defines the source and drain regions during the implant steps, as is conventionally known. In N-well areas, P-type implants which may be used are conducted to concentrations of preferably from about 1×10-14 to about 5×10-15 atoms/cm2 and at an energy from about 2 to about 5 keV to form P-type regions, using dopants such as boron (B) and/or BF2. Implants may be performed at a perpendicular angle to the substrate, or as is conventionally known, some implants may be pocket implants where the substrate is rotated and tilted to achieve a successful implant. N-type implants into P-well areas may be performed, using dopants such as As (arsenic) or Ph (phosphorous) to achieve a concentration such as from about 1×1013 to 5×1013 atoms/cm3 to a depth of about 500 to about 1200 Angstroms, using an energy of about 2 to about 5 keV for perpendicular implants, and for deeper or pocket implants, using an energy of about 100 to about 150 keV.
FIG. 5 depicts the substrate 101 following the completion of the transistors in both the memory and logic areas, the deposition of some interlevel insulation layers and the first steps in forming the capacitor over the substrate. Conventional ion implant and anneal steps have been performed to create the source or drain regions 114 for the planar transistors having gates 113, 115 and 119. Sidewall oxide 124 is shown deposited on the gates 113, 115 and 119. This oxide is produced by conventionally known deposition steps, for example, SiO2 is deposited using conventional deposition techniques, such as rapid thermal oxidation. The sidewall oxides may be formed from nitride, silicon nitride, oxide, silicon oxide, silicon oxynitride or composites such as ONO or NO composites.
FIG. 5 depicts the substrate 101 following formation of the gate sidewall regions 124 on the sidewalls for transistors having gate electrodes 113, 115 and 119 and following the deeper source/drain implants which complete the source and drain regions 114. Thus, the source and drain regions 114 each have a shallow area underneath the sidewall oxides which are adjacent and part of a deeper source drain region produced by conventional ion implantation and dopant anneal steps. These steps are conventional and well known to those skilled in the art.
FIG. 5 depicts the substrate 101 following the metal salicidation step and after a conformal layer of protective oxide is formed over the completed transistors having gates 113, 115, and 119 and polysilicon conductors 111, 117. As is known in the conventional art, resistance of conductive materials deposited on a substrate may be lowered by performing a self aligned silicidation, or salicidation, step over the materials. Conventional steps are used to form the salicidation layer 130 which is indicated as coating gates 113, 115 and 119 and source and drain regions 122, as well as the top surface of conductors 111 and 117 in FIG. 10. A metal layer is formed over the structure and heated to form silicide over the exposed polysilicon gates and conductors of FIG. 9, as well as the source and drain implant areas. The silicide structures 130 are preferably formed of cobalt silicide by applying a coating of cobalt and heating it, or forming Co-salicide, and/or titanium silicide by applying a coating of titanium and heating it, or Ti-salicide, other salicidation steps known and conventionally used may be performed. Following the salicidation step, a protective oxide conformal layer 126 is formed over the structure.
Following the formation of the transistors with gate electrodes 113, 115 119, interlevel insulation layers are formed to enable multiple metal layers, coupled by vias, to complete the device and allow for interconnections between metal layers. A capacitor 121 will be formed in the second layer of insulation in a recess. The process steps for forming the capacitor are as follows.
FIG. 5 depicts substrate 101 after a first insulating layer 157 is formed. Insulating layer 157 is deposited over the protective layer 126 and is initially fairly thick, from about 3000 to 5000 Angstroms, and may be deposited using conventional methods such as RTO, CVD, materials may include any number of known insulating layers such as, for example, CVD silicon dioxide, PSG, BPSG, high density plasma deposited oxide or others. Following this thick deposition, the layer 157 is machined to a thinner dimension and planarized using CMP techniques, as is known in the art and described above, and the layer 157 may then be further thinned by etching back using, for example, a plasma dry etch or further finely controlled CMP techniques. After CMP the layer 157 may be, for example, about 3000 Angstroms thick and the final thickness after the etch back may be, for example, about 600 to 1400 Angstroms over the gate electrodes 113, 115 and 117.
Following the deposition, CMP and etch back steps or other process steps to form layer 157, tungsten plugs 129, 131, 133, 135 and 137 are formed to contact the polysilicon conductors and gate electrodes and source or drain regions shown in FIG. 5. To form the tungsten plugs, conventional techniques are used. A stop layer, not shown, is formed over the insulator layer 157. This layer may comprise silicon nitride or silicon oxynitride, for example. Contact openings are etched into through the stop layer and the insulating layer and contacts are opened in the protective oxide 126 over polysilicon 111, 113, 115, 117, 119, source or drain regions 114 as shown in FIG. 5. The contact openings are then lined with a barrier material, also not shown, and filled with tungsten or another like material for conducting, which is deposited to fill the contact openings and extends onto the top surface of layer 157. The excess material is then removed again using CMP or a conventional etching technique to leave the structure of FIG. 5.
It is known in the art to form a MIM capacitor in the interlevel insulator layers by using a contact plug, here numbered 133, for example, as the electrical contact to the bottom plate of the capacitor later formed in a recess etched above the contact plug. In this particular example, the transistor having gate 119 will form a planar NMOS or PMOS type access transistor for the capacitor and the combination of the transistor and the capacitor (to be formed as described below) will form a 1T storage bit cell.
In FIG. 5 the substrate 101 is further depicted with a second level of insulator 155 formed. Layer 155 is formed using the same techniques as for insulator 157 although the thickness of this layer 155 may be more, and possibly much more, than that of layer 157, as the thickness of layer 155 will provide substantially for the vertical height of the capacitor and thus affect the values of capacitance that may be achieved. For example, layer 157 may be 3000-5000 Angstroms thick, or more or less for a given capacitor structure. After the second layer of insulator 155 is formed and planarized using CMP techniques, a stop layer (again not shown) of nitride or silicon nitride is formed over the oxide of layer 155 and contact holes are patterned and etched using conventional techniques, and vias contacting the via stacks 138, 136, 134 and 132 are opened and filled with tungsten plugs or like materials, to continue the vertical via stacks that contact the polysilicon layer and the source or drain regions. No opening is yet formed over the location of via 133, as that will be where the capacitor bottom plate is formed in the next steps.
FIG. 6 depicts the substrate 101 after the capacitor 121 is formed. Again the surface of layer 155 is patterned and etched to create the recess at 121, which will receive the bottom layer of the capacitor. The following steps complete the structure and describe the final steps in moving from FIG. 6 to the finished structure of FIG. 1. Capacitor 121 may be formed using a variety of conventional processing steps and materials. The bottom plate electrode may be formed, for example, by depositing tantalum nitride or titanium nitride conformally into the capacitor recess, the substrate is then subjected to a layer of photoresist over the conforming layer which is removed leaving only the TaN or TiN deposit within the recess, the top layer is stripped of photoresist and the deposited material. In a conventional process, the capacitor dielectric layer is then deposited which may be a high dielectric constant material and have a thickness of between 100 and 800 Angstroms, for example, and may include such dielectrics as tantalum oxide Ta2O5, aluminum such as Al2O3, hafnium, lanthanum, nitrides or the like, or conventional dielectrics such as silicon dioxide. Alternatively, a laminate of HfO2—Al2O3 may be used and formed, for example, by atomic layer deposition (ALD) process steps as described in “High-Performance MIM Capacitor Using ALD High-k HfO2—Al2O3 Laminate Dielectrics,” Ding et al, IEEE Electron Device Letters Vol. 24, No. 12, December 2003, which is herein incorporated by reference.
It is also known to increase the effective capacitance from a capacitor structure by using hemispherical grain (HSG) polysilicon or other grainy materials as the bottom electrodes, the dielectric and top electrodes are then deposited over this material in a conformal manner, the resulting capacitor plate area is subsequently increased due to the granular surface and thus the resulting capacitance is increased without a corresponding increase in silicon die area. So these approaches can be used in making the capacitor 153, if desired.
The capacitor 121 includes a top plate, preferably formed of two layers, another titanium nitride (TiN) or tantalum nitride (TaN) layer is formed over the dielectric layer and then a copper top plate is then formed using damascene processes and extending into the third insulating layer 153 as shown, these steps are conventional and will not be further described in detail here.
To form these layers over the dielectric, a layer of conductive material, usually the same as the bottom electrode, such as TiN or TaN, is deposited. Annealing steps may be used to complete the bond between the TiN and the dielectric. A metal layer, for example, an aluminum or preferably a copper layer is now deposited over the top electrode and filling the recess and is shown extending into the third insulator layer 153 where it is patterned to complete the capacitor. The copper top layer may be formed by electroplating or deposit and is removed by CMP steps to planarize and complete the pattern, a dual damascene process may be used. The top layer of the capacitor is then covered by the third layer of insulator 153, which is deposited and again subjected to CMP planarization.
To complete the structure shown in FIG. 1, vias are formed at the same location as 138, 136, 134, 132, and 177. Again contacts are opened and filled with tungsten plugs to complete the via stacks through the three insulating layers up to the metal layer. Conductors 151, 149, 147, 145 and 143 are possibly aluminum conventionally deposited and patterned, alternatively copper damascene processing may be used if the conductors are copper which is becoming the standard in the conventional art.
So again returning to FIG. 1, substrate 101 is depicted with a completed prior art structure including the MIM capacitor 121 formed within the interlevel insulator layers. Layer 153 is deposited over layer 155 and has metallization conductors 151, 149, 147 and 154 formed for contacting the source, drain and gate electrodes coupled to the via stacks. Metal conductor 143 contacts capacitor 121 by a via 177 formed through the third level of insulator material. Capacitor 121 may be conventionally formed of a bottom electrode of TaN or TiN, a high-k dielectric material including tantalum oxide Ta2O5, HfO2, AlTaOx, may be used and formed conventionally by deposition and annealing steps. HSG or roughened polysilicon can be used to increase the plate area and the resulting capacitance.
In order to get the most storage possible in an embedded RAM area of an integrated circuit, the various devices used to implement the RAM need to be as small as possible and very densely packed. Therefore, in addition to the storage capacitors themselves, the area required by the transistors used to access the memory capacitor, the access transistors, is also important. However, as the size of conventional MOS transistors is reduced with the scaling reductions of the overall process technology, conventional planar MOS transistor structures start to become less desirable. As the channel width of a MOSFET transistor is reduced certain “short channel” effects may occur where the source and drain regions remain electrically coupled even when the device is off, these effects can result in undesirable or even unacceptable performance, or errors.
Recently, an alternative MOS transistor topology, the finFET transistor, has been developed, as described, for example, in U.S. Pat. No. 6,729,619, to Chen et al, assigned to the assignee of the present invention and which is incorporated by reference; finFET transistors are also described in U.S. Pat. No. 6,413,802, to Hu, et al, which is also hereby incorporated by reference. The finFET transistor has a source, drain and gate region formed from silicon or other semiconductor “fins” which may be fabricated over any substrate or over an insulator, so that the transistor channel is not formed at the substrate surface but instead may be placed in layers produced above the substrate. Because the channel may be formed over an insulator (silicon-on-insulator or SOI) instead of the bulk silicon used in the conventional planar topology, in some applications the short channel effect is eliminated. The typical finFET also has at least two gate regions (formed on the sidewalls on either side of the fin) which enhances the performance of the device for given device surface area. To increase current carrying capacity it is possible to add additional gate regions to a device and so various capacity transistors may be produced.
FIG. 7 depicts an illustrative three-dimensional view of a finFET transistor device as known in the art. The device may be implemented over an insulator, over bulk silicon, or over silicon 201, which may be placed on an insulating layer as for SOI or SIMOX.
Other substrate materials such as silicon germanium, SiGe, or germanium may be used, of course. In FIG. 7 substrate 201 is shown and a silicon “fin” is provided, here numbered 203. This fin 203 will form the source and drain regions of the completed transistor, and the channel will form in the region between the source and drain. Gate oxide or dielectric 205 is provided, deposited over the sides of fin 203, and as shown in this example, the top of the source drain fin region 203. Because the gate oxide is deposited over two sides of the source drain, the device has multiple gates and may be referred to as a “multi-gate” device. A gate electrode 207 is shown formed over the gate oxide and in a direction which may be, for example, normal to the direction of the fin 203, so that the gate intersects the fin and overlies the fin in the channel region and the gate oxide. After the gate electrode is formed, conventional processing steps such as ion implantation may be used to dope the source and drain regions, also protective sidewalls may be formed to narrow and protect the fin, and other additional conventional processing steps may be used, which are not shown.
The device of FIG. 7 has many advantages over planar transistor devices, such as those formed in FIG. 1. The multiple gate structure greatly reduces or eliminates many problems of the prior art devices due to the reduction in scale, including the short channel effects and improves the drain induced barrier layer (DIBL) problems over the planar devices of the prior art. These effects are becoming more significant with reduced device scaling of current semiconductor processes and so the advantages of the finFET transistor likewise become more important.
A need thus exists for a single semiconductor manufacturing process which can be used to fabricate, on a single integrated circuit, the various elements of conventional planar logic MOS transistors or circuitry, MIM capacitors, and finFET transistor devices, for use in manufacturing fully integrated and highly functional integrated circuits using any or all of these elements. This need is addressed by the various methods and structures of the present invention.